Chapter 3: Phase-lock and Frequency Feedback Techniques

Latest Updates at http://www.ece.uah.edu/courses/ee426/ 3-1 Chapter 3: Phase-Lock and Frequency Feedback Techniques Figure 3-1 depicts a block diagram of a phase-lock loop (PLL). A considerable number of variations of this basic architecture have been proposed and used. However, many of these variants are mathematically equivalent to the loop described here. For reasons that will become clear as the topic is pursued, Figure 3-1 depicts what is often referred to as a short loop or a base band model of the PLL. The PLL depicted by Fig. 3-1 contains 1) a phase comparator (also known as a phase detector), 2) a loop filter, and 3) a voltage controlled oscillator (VCO). The phase comparator may be a simple analog multiplier. A different, usually more complicated, phase comparator may be used to exploit attributes (like a high input signal-to-noise ratio) of a given application. When present, the loop filter is low pass in nature, and it may be active or passive. The VCO oscillates with an instantaneous frequency that is functionally related to its control voltage e. The external reference signal supplied to the loop is modeled as the sum of a desired signal i 2Asin (t)  and an undesired additive noise component (t). In addition to random noise, the output of the phase comparator contains a component that quantifies the phase error   i v. This component is processed by the loop filter, and the results are applied to the input of the VCO. Hopefully, this controls the VCO phase and results in a small value of phase error variance.